Abstract

In 1983, B. Moszkowski introduced a first interval-interpreted temporal logic system, the so-called Interval Temporal Logic (ITL), as a system suitable to express mutual relations inside intervals for reasonings about digital circuits. In 1991, Halpern and Shoham proposed a new temporal system (HS) to describe external relations between intervals. This paper is aimed at proposing a basis-type combination of HS and a simplified ITL end extends it towards a multi-valued system—also capable of rendering a gradable justification of agents in a similar contexts of reasoning about digital circuits. This newly introduced system is semantically interpreted in the so-called fibred semantics.

Highlights

  • Before we propose the fibred semantics for combined formulae of Halpern–Shoham- Moszkowski Logic (HSM) already introduced, we need to elaborate at first a multi-valued logic for gradable verifiability (MVer) to integrate it with HSM

  • A fibred semantics has been proposed for combined formulae for this system

  • The analysis has been exemplified by some situations of an agent’s reasoning about processes in digital circuits. It was made in some coherence with the initial motivation of Moszkowski from his ‘Reasoning about digital circuits.’

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Summary

Introduction

The majority of realistic requirements-imposed on different IT-systems (they may refer to their liveness, safety, or activity.) often require temporal logic systems with nonpointwise semantics to be properly represented formally. Different context-oriented analysis and observations, f.e. from [1,2,3], visualized a need to explore interval-based semantics temporal logic systems in many engineering contexts, such as reasoning about digital circuits or specification of the instruction set processors. Moszkowski to propose a complex frame of the interval-based temporal logic system—recognized as ‘Interval Temporal Logic’ (ITL) and introduced in [4,5]. A potential application area of this formal system is determined by various devices, including the delay elements, adders, latches, counters, flip-flops, random-access memories, or a clocked multiplication circuit

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