A MPSoC cache design space exploration approach based on ABC algorithm to optimize energy consumption and performance

Abstract

Due to the constant growth of the embedded systems complexity and the increasing number of mobile devices, there is a increasing demand for low power multiprocessor platforms. It is known that the cache memory contributes with a representative percentage of energy consumption of a MPSoC processor, so that it is very important to use an optimal cache configuration for an embedded application in order to obtain low power consumption satisfying performance constraints. We propose an approach for cache design space exploration for embedded applications on MPSoCs platforms based on the multi-objective Artificial Bee Colony (ABC) algorithm. The proposed approach, called AbcDE, uses DoE analysis to reduce the design space exploration for finding the cache configuration that improves performance and power consumption. The proposed cache design space exploration approach has been evaluated using applications of Splash2 (FFT, Radix and Matrix multiplication) and Mibench benchmarks (Dijkstra). As a result, a L1 cache configuration into a low-power Pareto front has been obtained with a reduction of 42.3% in the exploration time. The mean number of simulations is 40.4% lower when compared with the original multi-objective ABC algorithm. All results were obtained for a 4-core processor platform.