A MOSFET Fabrication Using a Maskless Lithography System in Clean-Localized Environment of Minimal Fab

Abstract

A novel semiconductor manufacturing system minimal fab for customized semiconductor devices and micro electro mechanical systems on a half-inch wafer is developed. A distinct feature of the minimal fab is its clean-localized system eliminating a need of cleanroom environment. The clean level of the system is estimated by measuring separately each clean-localized component of the system including a minimal shipping case, wafer carrier, wafer load-lock system, and machine process chamber using a particle counter. The clean level of the system is analyzed to be in the ISO class 4, which is in the same class of a super clean room. In order to confirm the cleanliness needed for device fabrications, we employ a lithography system of the minimal fab consisting of a minimal coater, a minimal maskless exposure system using digital light processing technique, and a minimal developer hybridizing with conventional fab equipment to fabricate a metaloxide-semiconductor (MOS) field-effect-transistors (FET). The minimum gate-length of the MOSFET is realized at 1 μm with a good transistor characteristic. The measured interface states density of 2.33 × 10 10 cm -2 indicates that the whole processes during the fabrication are in the level of a sufficiently low contamination.