A MOS translinear cell-based configurable block for current-mode analog signal processing

Abstract

This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.