A monotonic SAR ADC with system-level error correction

Abstract

This paper presents a 10b 100 MS/s monotonic switching SAR ADC with system-level error correction of offset and noise tolerant technique. The error-correction structure involves a noise and offset controllable comparator and a redundant comparison cycle. The comparator operates in faster but larger offset and noise mode in MSB conversions, which is adjusted to slower but smaller offset and noise mode in LSB conversion after redundant cycle. At 10b resolution, the system is able to tolerate $$\pm 16$$±16 LSB offset and noise errors with different transistor mismatches in the comparator. The designed 0.13 $$\upmu$$μm 10b 100 MS/s SAR ADC incorporates an asynchronous control logic with manually controllable current source and speed acceleration technique. 9.54b ENOB is achieved at 100 MS/s under 3$$\sigma$$Â? offset mismatch condition while only 8.36b ENOB is achieved without error correction. The post-layout simulated ENOB and power consumption is 9.37b and 1.7 mW under 1.2 V supply, resulting in a 25.7 fJ/conversion-step figure of merit.