A Monotonic Low Power Thyristor-Based CMOS Delay Element

Abstract

A monotonic low power delay element, based on a CMOS thyristor, is proposed in this paper. A technique to reduce the charge sharing effect during switching is incorporated into the delay element to further enhance power supply insensitivity and to enlarge the range of the delay. Simulation results show that a delay from 177.6 ps to 7.494 ns is achieved and the average power consumed by the proposed delay element is from 5.786 μW to 80.5 μW with a unit CMOS inverter load. It exhibits a low power supply noise sensitivity and a temperature variation sensitivity, which are lower than the classical delay element, such as RC-based delay elements the chain of inverters and the differential delay element.