Abstract
According to the protocol of ISO/IEC 18000-6C, a monolithic UHF RFID transceiver is designed, in a standard 0.18gm RF CMOS process, in which a receiver, a transmitter and a frequency synthesizer are integrated. The direct-conversion receiver consists of a LNA, down-conversion mixers, DCOCs, LPFs and PGAs. A double-mode LNA is employed to meet the different requirements from listen and talk modes in the receiver. The direct-conversion transmitter is composed of a DA, up-conversion mixers, LPFs and PGAs, which supports three kinds of modulation, including DSB-ASK, SSB-ASK and PR-ASK, for the reader-to-tag communications. The ∑-Δ fractional-N frequency synthesizer is employed to produce high-quality I/Q local clocks for both the transmitter and the receiver. Post-simulation results show that, from a single power supply of 1.8V, a receiver sensitivity of −88dBm in listen mode, a receiver linearity (P1dB) of −2dBm in talk mode, a transmitter output power of 4.8dBm are achieved for the transceiver.
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