A module generator for high performance CMOS circuits

Abstract

The authors describe a timing driven approach to the problem of generating fast, area-efficient CMOS modules consisting of static combinational logic. This approach has its foundation in a unique CMOS layout style which offers good electrical properties suitable for implementing fast circuits. Circuit delays are optimized by the reduction of parasitic capacitance along the critical paths and by transistor reordering. By using a hybrid cost function in the simulated annealing optimization process, the layout area is optimized as well. Preliminary experimental results are presented. >