A modular exponentiation unit based on systolic arrays

Abstract

The described architecture of a modular exponentiation unit with systolic modular multipliers shows the following features: • simple VLSI-implementation based on systolic arrays, which are improved versions of the multipliers proposed in [Atrubi65] • two identical systolic arrays for the implementation of Montomery's modulo multiplication method • small data-paths because of the serial operation mode • the required number of clock cycles for a modular multiplication depends on the actual size of the operands and not on the size of the systolic arrays • By the separation of the cells in the middle of the systolic arrays, the modular multiplier can be reconfigured such that two modular multipliers are available for the multiplication of operands with half of the size. This can be used for the parallel processing of an exponentiation using a half-sized modulus (less security requirements) or for an application of the Chinese Remainder Theorem. • The throughput and the area demand of a chip for modular exponentiations based on this architecture can be widely effected by the selection of the design parameters (base b, number of modular multipliers, number of registers).