A Modified Proportional–Integral Loop Filter to Suppress DCO Noise in Digital PLL

Abstract

Although often analyzed as a second-order system, digital phase-locked loop (DPLL) is actually a third-order system because of the intrinsic latency in the loop filter. The extra pole introduced by this additional clock latency requires the loop filter bandwidth to be correspondingly reduced to ensure stability. In many applications, however, the loop bandwidth needs to be as wideband as possible, since the digital-controlled oscillator (DCO) is often the dominant source of noise. A modified proportional–integral (PI) loop filter is proposed to widen the loop bandwidth. The proposed loop filter employs an additional internal feedback loop that causes a third-order DPLL system to effectively behave as a second-order system. The proposed loop filter is derived based on the observer-controller DPLL. An intuitive explanation based on pole-zero analysis suggests that a wider loop bandwidth can be employed than in the conventional PI loop filter, because the proposed loop filter pushes the extra pole to a higher frequency than in the conventional loop filter. Similarly, for the same open-loop unity gain frequency and phase margin, the proposed loop filter can place the zero at a higher frequency, enabling greater attenuation of the DCO noise while achieving the same lowpass filtering of the reference clock noise as in the conventional loop filter.