Abstract

Capacitor voltage imbalance is a significant problem for three-level inverters. Due to the mid-point modulation of these inverter topologies, the neutral point potential moves up or down depending on the neutral point current direction creating imbalanced voltages among the two capacitors. This imbalanced capacitor voltage causes imbalanced voltage stress among the semiconductor devices and causes increase output voltage and current harmonics. This paper introduces a modified voltage balancing strategy using two-level space vector modulation. By decomposing the three-level space vector diagram into two-level space vector diagram and redistributing the dwell times of the two-level zero space vectors, the modified voltage balancing method ensures minimal NP voltage ripple. Compared to the commonly used NP voltage control method (using 3L SVM [9]), the proposed modified NP voltage control method offers a slightly higher neutral-point voltage ripple and output voltage harmonics but, it has much lower switching loss, code size and execution time.

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