Abstract

This paper offers a modified cross-coupled oscillator in 0.18 µm CMOS process. The argument in this paper is to provide an innovative approach to improve the phase noise. The proposed method offers an improved phase noise specification compared to the most traditional ideas in which the higher current dissipations is the key element of the phase noise improvement. The proposed oscillator is capable of an extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the peak voltage amplitude can verify the optimum performance of the proposed oscillator. This paper also presents a rigorous theoretical phase noise analysis of the proposed oscillator. A closed-form formula is derived of the phase noise in the 1/f 2 region. To verify the derived results, the results are validated against the simulations and illustrate good matches. The overall phase noise error has less than 3 dB error over the offset frequencies from the carrier. Post-layout simulation results at 2.4 GHz with an offset frequency of 1 MHz and 3 MHz show the phase noise of − 127.2 dBc/Hz and − 138 dBc/Hz, respectively, with the current of 1.2 mA in 1.8V supply. In addition, Monte Carlo simulation is used to ensure that the sensitivity of the proposed oscillator to process and frequency variations is very promising.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.