A Mismatch Compensation Scheme for Cyclic-pipelined ADC via Dynamic Element Matching Technique

Abstract

The inevitable capacitor mismatch due to the process variation is one of the major bottlenecks in high-resolution ADC (Analogue to Digital Converter) design. In this work we propose a new compensation strategy which adopts the DEM (Dynamic Element Matching) technique to conventional cyclic ADCs with minimum hardware cost. Theoretical analysis has been done first, and to the best of authors’ knowledge, it is the first time that the relation of the capacitor mismatch, output deviation and THD (Total Harmonic Distortion) has been mathematically established. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. Based on that we further analyse the effect of DEM in frequency domain, which effectively performs a harmonic shaping function to the original output spectrum. Simulation results show that the DEM compensation strategy can effectively boost the worst SINAD (Signal to Noise and Distortion Ratio) Figure from 68.8 dB to 89.5 dB (99.7% yield) under 0.1% capacitor mismatch and 32× oversampling ratio scenario.