Abstract
A chip scale package (CSP) using wafer scale processing was developed for a line of low cost, small form factor integrated circuits. The package uses polymeric repassivation and electrodeposited solder bumps connected by a unique conductor patterning method. The finished package resembles a common chip resistor. Reliability testing was used to optimize the bump design and the assembly methodologies. Field performance of more than 20 million packages has validated the test results.
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