A Miniaturization Approach Towards 40 GHz Integrated Single Chip Receiver System for MMW Communication Networks

Abstract

A full integration of single chip receiver system is remains to be a challenge in the area of millimetre wave (MMW) applications. In this paper, the integration of antenna, filter and CMOS low noise amplifier (LNA) is proposed which provides a new tri-design receiver system for MMW communication networks. A three-stage CMOS LNA is designed and integrated with co-design of filter and rectangular microstrip antenna which relaxes 50 ? impedance matching constraint for designing at 40 GHz. Moreover, the new tri-design technique heavily improves the overall system integration, minimizes the noise and reduces the chip area and thus saving overall cost of the system. A three-stage CMOS LNA design is simulated and layouted using 90 nm CMOS design kit in ADS.v.12. The simulation result of CMOS LNA shows an achievement of 3.8 dB noise figure, 15.8 dB gain and ?28 dB of return loss using proper impedance matching network. In addition, a theoretical analysis of three-stage CMOS LNA without using input---output matching network is done for the optimization of noise figure. A co-design of filter and patch antenna is also analyzed and integrated with CMOS LNA circuit. Finally, tri-design of receiver system demonstrates a peak gain of 25 dB and noise figure of 2.8 dB using proposed method.