Abstract

A two-phase, 2DEG-CCD intended for signal acquisition and delay with sample rates in the 1 to 20 GHz range is described. Signal delay versus clock frequency has been measured from 1 MHz to 13 GHz, verifying CCD operation. The input-to-output transfer function is linear for input powers ranging from -25 dBm to +2 dBm, with a 1 dB compression point at 4.5 dBm. The lower bound on CTE is 0.995 at 10 MHz and 4.02 GHz. CTE characterization results for clock frequencies between 4.02 GHz to 16.4 GHz qualitatively agree with those of two-dimensional transient simulations, which show that the charge packet transfers at saturation velocity. Simulations of a device incorporating an InGaAs channel predict that CTE greater than 0.9999 is attainable for clock frequencies up to 50 GHz. >

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