A Methodology to Emulate the Effect of EMI in Circuit Simulators for Wireline Communication Channel

Abstract

This letter presents a methodology to model the effect of electromagnetic interference (EMI) on the wireline communication channels. The proposed simulation methodology incorporates the effect of EMI on the circuit during the design phase in EMI-sensitive applications. It allows simple and faster EMI simulations at the SPICE level which minimizes the post-fabrication failures. A TEM (transverse electromagnetic) cell is used to emulate the effect of EMI on the test circuit as provided in the standard IEC-62132. An analytical model is presented to quantify the effect of induced voltage and current on a transmission line placed in the TEM cell. The developed model is experimentally verified for a frequency range of 1 MHz to 1 GHz. As an experimental study, the proposed model is used to validate the effect of EMI on the wireline communication channel transmitting a pseudorandom binary sequence (PRBS) data generated from an FPGA board at 1 Gbps data rate for a wide range of EMI powers and frequencies.