A Methodology for Reconstructing DSET Pulses from Heavy-Ion Broad-Beam Measurements

Takahiro Makino,Shinobu Onoda,Hirokazu Ikeda,Takeshi Ohshima,Kazuyuki Hirose,Daisuke Kobayashi

doi:10.3390/qubs4010015

Abstract

A table-based method for the estimation of heavy-ion-induced Digital Single Event Transient (DSET) voltage pulse-width in a single logic cell has been developed. The estimation method is based on the actual heavy-ion-induced transient current data in a single metal-oxide-semiconductor field effect transistor (MOSFET) used in the logic cell. The DSET pulse waveform in an inverter is obtained from which the pulse-width was estimated to be 420 ps. This DSET pulse-width value (420 ps) falls within the reasonable range of the DSET pulse-width distribution measured by the self-triggering flip-flop latch chain under heavy-ion irradiation test conditions.

Highlights

Digital single event transient (DSET) pulses are momentary glitch noises generated at logic gates by incident ions
Since the pulse-width of DSETs is a key parameter in determining the soft error rates in logic VLSIs, the DSET pulse-widths have been extensively measured by using logic cell chains, and specially built pulse capture circuits such as variable temporal latches, self-triggering latches/flip-flops, and high drive-capability output-buffers [2,3,4,5,6,7,8,9,10]
An analytical estimation method has been proposed to obtain the DSET pulse waveform generated in a logic cell from transient currents in a single metal-oxide-semiconductor field effect transistor (MOSFET) used in the logic cells [11,12,13]

Summary

Introduction

Digital single event transient (DSET) pulses are momentary glitch noises generated at logic gates by incident ions. Since the pulse-width (duration) of DSETs is a key parameter in determining the soft error rates in logic VLSIs, the DSET pulse-widths have been extensively measured by using logic cell chains, and specially built pulse capture circuits such as variable temporal latches, self-triggering latches/flip-flops, and high drive-capability output-buffers [2,3,4,5,6,7,8,9,10]. We can calculate the time variation of the logic out-put voltage from the time profile of the transient current with various supply bias conditions and static I-V characteristics of the other MOSFET in the inverter cell By using this table-based estimation method, we can obtain realistic waveforms of the DSET pulses without the need of any external circuit such as variable temporal latches, self-triggering latches/flip-flops, and high drive-capability output-buffers. We verify the pulse-width and our methodology by comparing our result to the previously measured DSET pulse-widths with a Snapshot circuit (self-triggering flip-flop latch chain)

Experimental

Experimental Results

Conclusions