Abstract
Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filter's hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods.
Highlights
Finite duration impulse response (FIR) digital filters are critical components in a wide spectrum of digital signal processing (DSP) operations and systems
We have developed further area efficiency results from a bit-serial filter core library for JBits along with an application-specific mapping and placement strategy that is presented in the paper
The placement director described in this paper extends the ability to explicitly define coordinates of JBits runtime parameterizable (RTP) cores within the field programmable gate arrays (FPGA) with methods that place cores in the FPGA in a folded fashion to maximize hardware density of a bitserial FIR filter core implemented in JBits
Summary
Finite duration impulse response (FIR) digital filters are critical components in a wide spectrum of digital signal processing (DSP) operations and systems. The placement director described in this paper extends the ability to explicitly define coordinates of JBits RTP cores within the FPGA with methods that place cores in the FPGA in a folded fashion to maximize hardware density of a bitserial FIR filter core implemented in JBits. Faster generation of the FPGA configuration bitstream obtained by avoiding conventional general-purpose mapping and placement tools is possible for a bit-serial FIR filter core by using the application-specific mapping and placement method for JBits.
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