Abstract
In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for different coding schemes and are using standard cell technology to verify the proposed methodology. The effectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated.
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