A Method to Reduce Jitter Due to Power Noise by Optimizing Loop Filter in PLL Based Clock Source

Abstract

The clock source is the most fundamental part of the microwave-based sensing system. Its phase noise and jitter performance directly determine the detecting accuracy of the entire system. Therefore, there are many applications that require a high-performance low-jitter clock source integrated on a single board together with other functional circuits. However, with the increased integration level of single-board circuits, the frequency of the onboard signal, and the requirements for miniaturization, the influence of power supply noise on the clock source generation module cannot be ignored. In other words, the power supply induced jitter (PSIJ) will arise inevitably to some extent. In addition, reducing the PSIJ has become increasingly difficult by optimizing the power supply network. This paper analyzes the output clock jitter of the phase-locked loop (PLL) based clock source under the influence of power supply noise and proposes a reasonable optimization design of the loop filter bandwidth to further suppress the impact of the power supply noise (PSN). The simulation results show that using the optimized loop filter, the output clock jitter can be attenuated by 78% in the case that the output has been influenced by the wideband noise and the bump power supply noise.