A method to design a comparator for sampled data processing applications

Abstract

The performance of a comparator is significantly affected by the time taken to determine the unequal bit location so as to decide greater than, less than and equal to condition. Consequently, the delay will increase with the number of bits of a comparator. The reduction in delay so as to improve performance can be achieved with the introduction of multilevel look-ahead circuit. In this work, a unique architecture of comparator with look-ahead circuit is introduced to reduce the worst case delay and to improve the overall performance. First, a multilevel look-ahead circuit is described to reduce the critical path delay effectively. Secondly, the realization of the comparator and multilevel look-ahead circuit using domino logic significantly reduces the complexity of the entire architecture. At first, a 4-bit unit cell is designed using domino logic. Thereafter, an 8-bit macro is realized using the unit cell. Further, 16-bit, 32-bit and 64-bit circuits are developed using the proposed 8-bit macro and multilevel look-ahead circuit. Simulation results show that the proposed 64-bit circuit has improved power dissipation compared to existing architectures. Moreover, the worst case delay has reduced significantly and the entire operation can be performed in a single clock cycle.