A method of analog circuit optimization using adjoint sensitivity analysis

Abstract

Analog circuit designing is an important aspect of VLSI chip design process. For the designing of analog circuits, electronic design automation tools need to be equipped with state-of-the-art efficient circuit analysis and optimization techniques. In this paper, a novel approach to optimize analog circuits (for gain, bandwidth and slew rate) is proposed using adjoint circuit analysis method. In this method an adjoint network of the original electrical (or electronic) circuit is constructed by using linearized circuit of the original electrical network in which MOS transistors are replaced by their small signal model. The objective function need to be analyzed for the optimization of analog circuit is evaluated using linearized circuit and its adjoint network (circuit) along with steepest descent method to find the next set of design parameters to optimize circuit in the design space. Barzilai and Borwein method is used to find the direction of design parameter vector during circuit optimization process. In this paper a basic cascode amplifier circuit has been designed at 180nm technology to prove the correctness of proposed method. To prove the effectiveness of the proposed approach, a two-stage operational amplifier circuit is also designed for gain optimization subject to a variety of design conditions and constraints. The solution of these circuits, designed with the optimized parameters calculated using our proposed method, matches with the solution of cascode amplifier and two-stage operational amplifier circuits designed using Mentor Graphics tool Pyxis (Eldo).