Abstract
To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.
Highlights
In the past several decades, multilevel power topologies have increasingly been used in high-power, medium-voltage drives [1,2]
Several strategies have been proposed for multilevel converters, such as sinusoidal pulse width modulation (SPWM), selective harmonic elimination pulse width modulation (SHEPWM), and space vector pulse width modulation (SVPWM)
In a five-level NPC/H bridge inverter, the common-mode voltage UCMV is expressed as Equation
Summary
In the past several decades, multilevel power topologies have increasingly been used in high-power, medium-voltage drives [1,2]. The NPC/H bridge topology has two crucial problems: an imbalance in capacitor voltages in three phases and a requirement that the common-mode voltage be suppressed. In [15], for a five-level, diode-clamped (DCC), the duty cycles are calculated for the redundant states and adjusted between two zero vectors converter (DCC), the duty cycles are calculated for the redundant states and adjusted between two to control the capacitor voltages This method is not suitable for the NPC/H bridge topology because zero vectors to control the capacitor voltages. Another author other one operates with the conventional three-level SVPWM This measure can inhibit the CMV to proposes a strategy called hierarchical model predictive voltage control (HMPVC) [18], which can. A dual-pulse-mapping algorithm is proposed for the simultaneous suppression of of DC-side capacitor midpoint potentials and CMV in five-level NPC/H bridge inverter. NPC/H bridge topology, which makes the NPC/H bridge topology play a better role in high-voltage and high-power
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