Abstract
Decimal multiplication is one of the most extensively used and complex computations in many commercial and financial applications. This paper presents a novel design for a single constant decimal multiplier with constant coefficients of 10 to 19. The parallel generation of partial products is performed using BCD-8421 or BCD-4221 encodings. Decimal multioperand addition has been used for partial product reduction stage. Also, a redundant to none-redundant converter for the last stage of the multiplier is proposed. To evaluate the architecture, a VHDL model is presented and synthesized in TSMC 130nm technology. The results of the implementation show that the parallel single constant decimal multiplier has an interesting delay, area, power consumption, and PDP compared to others decimal multipliers.
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