A Method for Reducing the Register Effect for Modular Data Formats

Abstract

The substantiation of the author's method of reducing redundancy from the register effect when placing the components of a tuple representing a numerical value in a modular format designed for storage, transmission and processing in modular arithmetic in a specialized SIMD processor of parallel structure is given. Modular coding allows to obtain parallel execution of ring operations in independent computing paths. This, according to Amdahl's law, accelerates the execution of the computational process on multiprocessor computing systems or on multiple cores. Modular data formats are not consistent with the binary bit grid of a multiprocessor computer. In homogeneous binary registers designed to display modulo deductions, redundancy occurs because not all possible binary combinations in a digital register are used to display data. The method is based on the redistribution of the redundancy of digital registers used to display the components of the modular tuple, which allows to reduce to zero the register effect and redundancy of the representation of the components of the tuple. This makes it possible to obtain a dense packing of components of vector modular formats in homogeneous digital registers, which makes the development of SIMD architecture computers processing data in computer modular formats promising. The simulation results allow us to obtain mutually simple bases of the modular number system that meet the conditions of a new patented method for the complete elimination of redundancy.