A memory-efficient architecture for intra predictor and de-blocking filter in video coding system

Abstract

In the hardware architecture of the H.264/AVC video coding systems, the storage size of the intra predictor and de-blocking filter occupies a great portion of the internal memory size in the video coding. However, the higher resolution video costs huge internal memory size to store pixels to predict block data and eliminate the blocking effect, especially for the next-generation video applications which target resolution is Ultra-HD (8Kx4K). In this article, a memory-efficient architecture for intra predictor and de-blocking filter has been proposed which can roughly reduce up to 19% internal memory usage to efficiently reduce the decoder size and power consumption, and the sequential-interleaving memory architecture has also been adopted in the proposed architecture to solve the memory access conflict during video decoding. A test module is designed for the proposal and operates at 200 MHz for real-time processing with 85.1 K gates and 8.4 KB SRAM in 90nm CMOS technology.