Abstract
There is an increasing interest among real-time systems architects for multi- and many-core accelerated platforms. The main obstacle towards the adoption of such devices within industrial settings is related to the difficulties in tightly estimating the multiple interferences that may arise among the parallel components of the system. This in particular concerns concurrent accesses to shared memory and communication resources. Existing worst-case execution time analyses are extremely pessimistic, especially when adopted for systems composed of hundreds-tothousands of cores. This significantly limits the potential for the adoption of these platforms in real-time systems. In this paper, we study how the predictable execution model (PREM), a memory-aware approach to enable timing-predictability in realtime systems, can be successfully adopted on multi- and manycore heterogeneous platforms. Using a state-of-the-art multi-core platform as a testbed, we validate that it is possible to obtain an order-of-magnitude improvement in the WCET bounds of parallel applications, if data movements are adequately orchestrated in accordance with PREM. We identify which system parameters mostly affect the tremendous performance opportunities offered by this approach, both on average and in the worst case, moving the first step towards predictable many-core systems.
Highlights
In the last decade, embedded systems embraced heterogeneous designs, where a powerful, general-purpose host processor is coupled to massively parallel accelerators featuring hundreds of simple and energy-efficient cores, grouped into clusters to achieve architectural scalability [1], [2], [3], [4]
Using a representative embedded heterogeneous system, namely, the TI Keystone II EVMK2H board [14], we demonstrate the great potential of the PRedictable Execution Model (PREM) execution model for achieving predictable execution times on embedded multi-/many-core platforms
The complexity of worst-case timing analysis on these architectures prevents their adoption in the real-time domain due to pessimistic and over-conservative worst-case execution time (WCET) predictions
Summary
In the last decade, embedded systems embraced heterogeneous designs, where a powerful, general-purpose host processor is coupled to massively parallel accelerators featuring hundreds of simple and energy-efficient cores, grouped into clusters to achieve architectural scalability [1], [2], [3], [4]. We would like to show that it is possible to reduce and/or more tightly upper-bound the duration of memory contentions by using recently proposed memory-aware execution models, enhancing the predictability of multi-core real-time systems. We apply the PREM model to heterogeneous multi-/many-core embedded platforms with explicitly managed memories, enabling a predictable exploitation of the tremendous performance potential of these promising devices. We model the principal system-level components that influence the execution time of parallel tasks, identifying how the WCET varies depending on the number of cores These results constitute a first step towards the definition of the necessary models and system background to develop sound memory-aware scheduling algorithms and schedulability tests for heterogeneous many-core systems based on PREM.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
