A memory size reduction method of pipelined IFFT processor for OFDM systems

Abstract

In this paper, we propose a new IFFT design method for orthogonal frequency division multiplexing (OFDM) systems to reduce the memory size of IFFT based on a combined integer mapping of three IFFT input signals: modulated data, pilot and null signals. The proposed method focuses on reducing the size of memory cells in the first two stages of the pipelined architectures since the first two stages require 75% of the total memory cells. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than about 35% reduction in gate count and about 34% reduction in power consumption compared with conventional IFFT design.