A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW/SW Partitioning on Reconfigurable MPSoCs

Zhongfu Guo,Bo Zhao,Xingming Zhang

doi:10.1109/access.2019.2934390

Abstract

Hardware/software (HW/SW) partitioning and scheduling are the crucial steps in HW/SW co-design. They have a strong effect on performance, area, power and the system itself. In this paper, a memory-reinforced tabu search algorithm with critical path awareness (MTSP) is proposed for solving the HW/SW partitioning problem. First, the critical path (CP) algorithm can locate the critical task queues and output a reduced task graph. Second, the solution to a heuristic algorithm (HA) is used as the initial solution. Third, by introducing hash technology, adding dual memory tables improves the search strength and effectiveness of the tabu search, and the experiment is completed by priority scheduling. MTSP especially has good performance in large task graphs, while it can greatly improve system performance, especially in the case of generating a large communication penalty. The experimental results show that the average improvement over the latest efficient hybrid algorithm is up to 5%. The improvement in algorithm searching time is 66% in comparison to the popular algorithms cited in this paper.

Highlights

As the density of transistors increases, multiple processors system on chip (MPSoC) came into being in order to combat the power wall: with increased processor clock speeds for faster performance came increased power output [1]–[3]
Input: SHA-Initial solution generated by the algorithm heuristic algorithm (HA); Output: Sbest -the best-so-far solution found by MEMORY-REINFORCED TABU SEARCH ALGOTITHM (MTS); /∗q indicates the neighborhood size.∗/ Begin 1 Slocal := SHA, and Sbest := SHA; 2 If area A is enough for all tasks performed on the hardware processing elements (PEs)
In order to make a fair comparison with tabu search simulated annealing (TSSA) and genetic algorithm tabu search (GATS), considering that these algorithms are heuristics rather than exact algorithms, a general test benchmark is necessary, and our implementations are based on the same type of task graph as used in [21]

Summary

INTRODUCTION

As the density of transistors increases, multiple processors system on chip (MPSoC) came into being in order to combat the power wall: with increased processor clock speeds for faster performance came increased power (and heat) output [1]–[3]. The traditional performance improvement method for MPSoC computing resources is the optimization of task partitioning [5], [6] and scheduling algorithms [7], [8]. HW/SW partitioning [9], [13], [14] is the crucial step during HW/SW co-design, and the HW/SW partitioning algorithm determines which components are implemented in hardware and which components are implemented in software [15] It can guide the design and configuration of computing resources, reducing the overall power to achieve regional optimization; second, the system can be optimized to obtain the maximum acceleration. When there are multiple termination nodes, adding Vend after all the termination nodes ensures that the DAG has a unique start node and termination node, Vstart and Vend execution time are 0, and the communication overhead with the task graph is cost free. Check svi; tasks with short software execution time are preferred

PROBLEM P AND RELATED METHODS

RESULTS AND DISCUSSION

CONCLUSIONS AND FUTURE WORK