A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC

Abstract

In this paper, a memory interleaving and interlacing VLSI architecture for deblocking filter in H.264/AVC is proposed. Many literatures and the results of the chip implementation show that the memory organization dominates the hardware cost, the throughput rate, and the external memory bandwidth of the deblocking filter. Hence, we also discuss three different levels of the data-reuse scheme for deblocking filter in this paper. In order to increase the throughput, we propose the memory interleaving techniques to arrange data in the on-chip memory and access the data in both horizontal and vertical filters efficiently. We also utilize the hybrid schedule for 2-D processing order and the memory interlacing configuration to reduce the total on-chip memory size and to accomplish the Level B data-reuse scheme. According to proposed memory interleaving organization, memory interlacing configuration and hybrid schedule of the 2-D process order, our architecture only utilizes a half of the traditional memory size to boost the throughput and reduce the bus memory bandwidth.