Abstract
The motion estimation is the most complex module in a video encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high-definition videos. The throughput problem can be solved increasing the parallelism in the internal operations. The external memory bandwidth may be reduced using a memory hierarchy. This work presents a memory hierarchy model for a full-search motion estimation core. The proposed memory hierarchy model is based on a data reuse scheme considering the full search algorithm features. The proposed memory hierarchy expressively reduces the external memory bandwidth required for the motion estimation process, and it provides a very high data throughput for the ME core. This throughput is necessary to achieve real time when processing high-definition videos. When considering the worst bandwidth scenario, this memory hierarchy is able to reduce the external memory bandwidth in 578 times. A case study for the proposed hierarchy, using32×32search window and8×8block size, was implemented and prototyped on a Virtex 4 FPGA. The results show that it is possible to reach 38 frames per second when processing full HD frames (1920×1080pixels) using nearly 299 Mbytes per second of external memory bandwidth.
Highlights
Nowadays, several electronic devices support high-definition digital videos
The presented numbers consider the way of our memory hierarchy reuse data, keeping data previously loaded into local memories and registers
This paper presented a memory hierarchy model for fullsearch motion estimation aiming to reduce the external memory bandwidth requirement
Summary
Several electronic devices support high-definition digital videos. Applications like internet and digital television broadcasting are massively supporting this kind of media. The motion estimation requires, besides the high processing throughput, a very high bandwidth of external memory to realize its operations in real time when considering full HD videos (frames with 1920 × 1080 pixels) [3]. The motion estimation presents the highest demand for external memory bandwidth, and it shares the external memory interconnection subsystem with others encoder modules like the motion compensation, the intraframe prediction and the deblocking filter. In this context, it is important to explore methods and architectural solutions which minimize the number of external memory accesses.
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