A Mathematical Formulation of the Wire Resistance Problem in Memristor Crossbars

Abstract

Memristor crossbars have become promising candidates for accelerating linear algebra computation. The array structure allows strong parallel computing capability and enables data storage for reducing the energy cost due to data migration. Despite their fascinating potentiality for neuromorphic applications, the resistance of metal wire can detrimentally affect the performance of the circuit. This phenomenon is particularly enhanced when dealing with large crossbars. Several schemes to mitigate this issue were proposed, but an exact solution of the wire resistance effect has never been provided. To understand the degradation of the system's accuracy due to the presence of wire resistance, this work provides a closed-form mathematical description of the wire resistance contribution when performing a matrix-vector multiplication. This formulation allows to evaluate the influence of both vertical and horizontal interconnecting lines and enables the correct computation of the effective conductance matrix and the voltage drop. Future works aim to combine these results with the current approaches used to compensate the output deviation and to provide mathematical tools that mitigate this critical systematic effect.