Abstract
A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.
Highlights
The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture
A Ring Oscillators (ROs)-based TDC was developed to be integrated in pixel detectors for HEP and medical imaging applications
Two models were developed for the analysis of the proposed solution architecture and to demonstrate that the integration of the buffers into the feedforward paths is useful to reduce the impact of their mismatch on the linearity of the system
Summary
The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. The oscillator is integrated in a event-by-event selfcalibration system that allows avoiding any PLL-based synchronization For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy. The matrix of the detector chip can be divided in sub-matrices: in the example of the figure, they are composed of 2 x 2 pixels and each of them is connected to a different TDC channel through the fast-OR blocks, together with the corresponding pixels of other sub-matrices. As will be shown, the proposed converter is characterized by a PLL-less architecture, a useful solution to further reduce power consumption, complexity and area, integrating more TDC channels in a single chip. A set of offset parameters will be applied to the outputs of the system (given by Eq 2.12-2.14 as it will be explained in Section 2) in order to minimize the standard deviation of the measured values
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