Abstract
The architecture of an electronic mesh array for image processing by simulated annealing is described. On the algorithm side, it is well suited to cases where the input data is a grey-level picture, the output data is a binary picture, and the energy model is a generalization of the Ising model with external field. The example of digital halftoning is covered. On the implementation side, this architecture is intended for VLSI monolithic integration. Its PE uses both analog and digital devices, and is specifically designed to take advantage of an optical random number generator. These features result in a compact processor array with near real time performances for binary pictures stochastic relaxation.
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