A mapping algorithm for embedded coarse-grained reconfigurable processor

Abstract

This paper proposes a novel VLSI architecture of an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained Reconfigurable Cell Array (RCA). This processor can be reconfigured dynamically targeted at different media-processing applications. An algorithm based on loop pipeline technology is presented to address the compilation issue for the proposed architecture, which can effectively maps the computation intensive loops onto the RCA. The proposed VLSI architecture and the mapping algorithm have been verified with integer Discrete Cosine Transform (DCT) and Motion Estimation of H.264 in FPGA. The performance of the reconfigurable processor is 3.81 times better than TI DSP TMS320DM642.