A Magnetic Reconfigurable Ternary NOR/NAND Logic for Logic-in-Memory Applications

Abstract

Logic-in memory has emerged as a promising solution to reduce the significant time gap between processor and memory. Simple logics such as NOR and NAND can be embedded in the memory for the purpose of data processing. Besides, ternary logic has been suggested to reduce the interconnects and the complexity of operations. In this paper, a reconfigurable ternary NOR/NAND logic compatible with ternary memories has been proposed. This scheme exploits magnetic tunnel junction as a nonvolatile memory element and a variable resistance, and carbon nanotube field-effect transistor for designing the peripheral circuits to achieve performance and efficiency. The proposed circuit is simulated using HSPICE and the results have validated the correct operation and high performance of the proposed design. Furthermore, the proposed designs are exploited in image processing applications to evaluate their performance in real applications, which gain averagely 52% improvement in the case of data loss.