A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 ms/s

Abstract

The problem of realizing low-voltage SC circuits is addressed. The case of using standard CMOS technology without on-chip multiplication is focused on. In this situation, a tradeoff between a high sampling frequency and a large output swing is present. In fact the switched-op-amp technique guarantees rail-to-rail output swing but at a low (<4 MHz) sampling frequency. The use of standard structures at a reduced output swing allows one to operate at a much higher sampling frequency (/spl ap/40 MHz). This concept is demonstrated here with experimental results from a 1.2-V 600-/spl mu/W SC double-sampled pseudodifferential sample-and-hold (S&H) circuit realized in a standard 0.5-/spl mu/m CMOS technology without using an on-chip voltage multiplier. With a 600-mVpp signal at 2 MHz using a 40-MHz sampling frequency, the sample-and-hold exhibits a total harmonic distortion better than -50 dB and a CMR better than -40 dB.