A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Abstract

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses, including, among others, industrial, automotive, and medical equipment. The impressive growth in photodetector applications is closely linked to the development of CMOS technology, which now offers inexpensive and efficient analog and digi-tal signal processing capabilities. Detectors are often integrated with their respective front end and application-specific digital circuit on the same silicon die, forming complete systems on chip. In some cases the detector itself is not on the same chip but often part of the same package. However, this trend of co-integration of analog front end and digital circuits complicates the design of the analog part. The ever-decreasing supply voltage and the smaller transistors in advanced processes (which are driven by the development of digital cir-cuits) negatively impact the performance of the analog structures and complicates their design. For photodetector systems, the effect most importantly translates into a degradation of dynamic range and signal-to-noise ratio. One way to circumvent the problem of low supply voltages is to shift the operation from voltage domain to time domain. By doing so, the signal is no longer constrained by the supply rails and analog amplification is avoided. The signal takes the form of a time-based modulation, such as pulse-width modulation or pulse-frequency modulation. Another advantage is that the output signal of a time-domain photodetection system is directly interfaceable with digital circuits. In this work, a new type of CMOS-compatible photodetector displaying intrinsic light-to-time conversion is proposed. Its physical structure consists of a MOS gate interleaved with a PN junction. The MOS structure is acting as a photogate. The depletion region shrinks when photogenerated carriers fill the potential well. At some point, the anode of the PN structure is de-isolated from the rest of the detector and triggers a positive-feedback effect that leads to a very steep current increase through the PN-junction. This translates into a signal of very high amplitude and independent from light-intensity, which can be almost directly interfaced with digital circuits. This simplifies the front end circuit compared to photodiode-based systems. The physical behavior of the device is analyzed with the help of TCAD simulations and simple behavioral and shot-noise models are proposed. The device has been co-integrated with its driver and front end circuit in a standard CMOS process and its characteristics have been measured with a custom-made measurement system. The effect of bias parameters on the performance of the sensor are also analyzed. The limitations of the device are discussed, the most important ones being dark current and linearity. Techno-logical solutions, such as the implementation of the detector on Silicon-on-Insulator technology, are proposed to overcome the limitations. Finally, some application demonstrators have been realized. Other applications that could benefit from the detector are suggested, such as digital applications taking advantage of the latching behavior of the device, and a Photoplethysmography (PPG) system that uses a PLL-based control loop to minimize the emitting LED-current.