A Low-Temperature Process for Device Quality Si/SiO2 Interfaces On Si(111)

Abstract

Device-quality Si/SiO 2 interfaces with an interface trap density as low as ∼2 × 10 10 cm −2 eV −1 were formed on Si( 111) surfaces by a low-temperature, two-step oxidation/deposition process using a remote plasma enhanced CVD system. The micromorphology of the initial Si(1 11) surface was changed i) by controlling the roughness of the initial Si surface through the pH of HF/NH 4 F treatments, and ii) by an introduction of surface steps using Si(111) wafers that were cut off the axis in the direction. When the Si wafer was subjected to a pre-deposition rinse in a 40 wt-% NH 4 F solution to develop an atomically smooth surface, the SiO 2 /Si(111) interface displayed a midgap interface trap density, D it , of 2∼3 × 10 10 cm −2 eV −1 with Al as an electrode material. The Dit values increased systematically up to about 1 × 10 11 cm −2 eV −1 as the pH of the HF/NH 4 F treatment was decreased. The density of surface steps had a lesser effect on D it . MOS capacitors with an n-type poly-Si electrode also showed D it of ∼2 × 10 10 cm −2 eV −1 . The effects of the hightemperature processing associated with poly-Si deposition and doping are discussed in conjunction with our recent study on second harmonic generation from the SiO 2 /Si interfaces.