A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA

Abstract

ABSTRACT The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.