A low-power single-slope analog-to-digital converter with digital PVT calibration

Abstract

A low-power single-slope analog-to-digital converter (SS ADC) is presented that uses an ultra-low-power reference current to achieve nano-watt power dissipation and a digital calibration function to compensate for the effect of process, voltage and temperature (PVT) variations. It converts two analog reference voltages into digital reference codes before it converts the input voltage into an input digital code. The SS ADC is tolerant to PVT variations due to the processing of the input digital code and two reference codes in the digital domain. A prototype was fabricated in the 180 nm CMOS process. Measurements demonstrated that it achieved a signal-to-noise-and-distortion ratio of 40.8 dB and an effective number of bits of 6.49 at a sampling rate of 800 S/s. It dissipated 174 nW in analog power and 36.5 nW in digital power, corresponding to the figure of merit for the 293 pJ/conversion-step.