A low-power, low-noise CMOS amplifier for neural recording applications

Abstract

There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5/spl mu/m CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2/spl mu/Vrms and a power dissipation of 80/spl mu/W while consuming 0.16mm/sup 2/ of chip area.