Abstract
Knowing the phase jitter is helpful for improving the design quality of a GHz clocking system. In this paper, we present how to design a low-power and low-cost built-in jitter measurement (BIJM) circuit in 28 nm CMOS for monitoring the on-chip clock jitter in DDR4-2133. The implementation and measurement results show that the proposed BIJM achieves a 77% power reduction and a 7% area reduction compared to the state-of-the-art design.
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