A low-power high-performance current-mode multiport SRAM

Abstract

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-/spl mu/m CMOS process have shown 2.8 to 9.9/spl times/ in energy savings and 1.02 to 6.36/spl times/ reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32/spl times/64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach.