A Low-Power Front-End with Compressive Sensing Circuit for Neural Signal Acquisition Designed in 180 nm CMOS Process

Abstract

Multi-channel data acquisition of bio-signals is a promising technology that is being used in many fields these days. Compressed sensing (CS) is an innovative approach of signal processing that facilitates sub-Nyquist processing of bio-signals, such as an electrocardiogram (ECG) and electroencephalogram (EEG). This strategy can be used to lower the data rate to realize ultra-low-power performance, As the count of recording channels increase, data volume is increased resulting in impermissible transmitting power. This paper presents the implementation of a CMOS-based front-end design with the CS in the standard 180 nm CMOS process. A novel pseudo-random sequence generator is proposed, which consists of two different types of D flip-flops that are used for obtaining a completely random sequence. The power consumed by the bio-signal amplifier block is 2.35 μW. The SAR-ADC block that is designed to digitize the amplified signal consumes 277 μW of power and the power consumption value of the pseudo-random bit sequence generator (PRBS) is 344.2μW. The sampling rate of PRBS block is 611.76 Kbps. We have considered collecting neural data from the 32 channels, and achieved an 8.5X compression rate. The low power consumption per channel confirms the importance of the proposed approach for multiple channel high-density neural interfaces.