A low-power dual threshold voltage-voltage scaling technique for domino logic circuits

Abstract

As domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very commonly used for high-performance processors; however, the average power consumption of the domino circuits is larger than that of the static circuit. This power dissipation problem needs to be solved for the domino circuits. The power consumption of conventional CMOS circuits is composed of dynamic and static parts. The static (leakage) power of domino logic increases exponentially with the scaling of the threshold voltage (Vt) and gate oxide thickness (tox), the dual threshold voltage technique (DTV) is one of most popular techniques to suppress leakage power. Dynamic power of the circuit is greatly reduced by Voltage Scaling (VS) technique. By merging the above techniques a new technique called Dual Threshold Voltage - Voltage Scaling (DTVS) technique which further reduces total power consumption of domino circuits. To verify the above technique, the basic gates and adder circuit has been implemented with DTVS, with DTV alone and without any technique. The power consumption was analyzed by implementing the circuit in UMC 90nm CMOS technology. The 67% of power reduction is possible with DTVS technique. Mentor Graphics ELDO and EZ-wave are used for simulations.