Abstract
In this paper we present an integrated circuit implementation of a soft DSP based low-power digital filter in 0.35 /spl mu/m, 3.3 V CMOS process. Soft DSP is a low-power technique that employs voltage overscaling (VOS) and algorithmic noise-tolerance (ANT) to push the limits of energy-efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1 db loss in SNR for a wide range of filter bandwidths (0.05 f/sub s/-0.25 f/sub s/, where f/sub s/ is the sampling frequency).
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