A Low-Power Digital Control Core with High-Speed SPI Slave for Phased Array Application in 40nm CMOS

Abstract

A low-power digital control circuit with high-speed serial peripheral interface (SPI) is presented in this paper, which enables fast and flexible configuration of integrated multi-channel phased arrays. The addressable digital control circuit enables amplitude, phase and other control registers configuration. The SPI enables full-duplex, one-to-many and high-speed communication between the master and slaves. In addition, if a transmission error occurs, it will be detected and reported by internal error mechanisms. The proposed circuit has been fabricated and tested in 40nm CMOS. The measurement results show that this digital circuit can stably work at a clock rate of 100 MHz with 0.1 mW power consumption and 0.036 mm2 silicon area overhead. The high-speed and low-power digital circuit is expected to be widely used in the future integrated multi-channel phased array designs.