A low-power clock generator based on digital DLL for high speed pipelined ADCs

Abstract

This paper presents a low-power clock generator based on digital delay locked loop (DLL) for high-speed and high-resolution analog-to-digital converters (ADCs). A novel structure for the phase detector and delay controller is adopted to eliminate dithering and false locking of the DLL. The operation frequency range of the DLL is 30MHz∼250MHz, and the corresponding locking time is about 66.4us and 730ns, respectively. The proposed clock generator consumes 7.7mW from a 1.8-V power supply. A 250MSPS, 10-bit charge domain pipelined ADC adopting the DLL is fabricated in SMC 0.18μm CMOS process and achieves a SNDR of 56.7 dB.